For several decades it has been customary to mount a semiconductor die inside a discrete package and to mount the package on a printed circuit board, (PCB). Within the package, wire bonds have been commonly used to connect from input/output (I/O) pads on the die to terminals on the package, plus soldered connections (through-hole or surface mount) between external package terminals and corresponding terminals on the PCB.
In recent years, a new method of assembly called “direct chip attach” or “flip chip” has been used for high-speed integrated circuit (IC) chips. In the most popular flip chip method, I/O pads on the die are bumped with solder material. The die is attached to lands on a substrate by flipping the die, aligning it to the substrate, and melting (reflowing) the bumps. Flip chip attachments are preferably used for higher-speed circuits because the parasitic impedance of the connections is generally much less than for wire-bonded connections. However, direct attachment from chip to board is not typically achieved; an intermediate substrate with redistribution circuits is usually required. The redistribution circuits map signals between the fine features of the chip and the coarser features of the board.
Semiconductor chips are normally tested at wafer sort wherein metal probes on a probe card are brought into contact with each of the I/O pads, thereby connecting them to corresponding nodes within a tester. By this means they are tested functionally and parametrically. Functional testing is used to verify logic behavior, and parametric testing is used to verify that analog quantities like supply current and leakage current are within bounds. Typically, wafer sort will be effective in rejecting around 90% of the defective chips, and the remaining 10% will be rejected at “class test” which is a final test at the component level. Class testing is usually performed on packaged parts and typically includes full speed functional tests, not limited by the high parasitic impedance of the probes. However, the discrete packaged part option may not exist for some modern packaging approaches such as chip-on-board (COB), or stacked die packages. In the case of COB, a rework procedure may allow the board to be corrected, although such repair will typically be time-consuming and costly. For the case of the stacked die package, the whole assembly must be rejected, because it is typically not possible to replace any defective chips in the stack. Herein lies the motivation for the temporary socket of the current invention. If a temporary socket exists that allows full speed operation, it can be used to perform a class test or final test at either the wafer level or on separated die to produce known good die (KGD). The confidence level in these KGD will be higher than is currently achievable because the testing will have been more thorough. This higher confidence level translates into lower system cost because of yield factors, wherein some percentage of completed assemblies will be wasted if a “KGD” turns out to be defective.
A similar temporary socket may also be used for burning-in singulated die (diced and separated from a wafer), wherein the die is stressed at temperature and voltage extremes that are typically employed to identify marginal components. Performing burn-in using conventional wafer sort equipment is difficult, requiring hot chucks, long test times, and a massive number of connections between the I/O pads of a full set of chips on a wafer and their corresponding tester nodes. The temporary socket provides a way for KGD to be produced with a high level of confidence; when assembled into higher-level components they are guaranteed to be good, except for potential assembly issues not relating to chip quality.
Processes have been developed for fabricating copper mesas or pillars onto the I/O pads of IC chips. Like solder balls used in ball grid arrays (BGAs), copper mesas are “bumps”. However, in contrast to the stiffness of solder balls, they can be produced with a length:diameter ratio that provides flexibility at the connection, an important advantage for reliable connections. One proven fabrication method is to electroform the mesas in a plating solution, using photo resist to define the columns to be plated. Special photo resists have been developed for this purpose, such as SU-8 2000, available from Microchem, Newton, Mass., USA. This resist can be patterned with a thickness of 60 μm for example, using a single spin-coating. The sidewalls of the resist can be essentially vertical, and special techniques for stripping the thick resist are available. Under bump metallizations (UBMs) have been developed to provide reliable inter-metallic junctions between aluminum or copper pads and the plated mesas. Also, the plating process is capable of electroforming mesas with aspect ratios as high as 10:1, especially using periodic pulse-reversing power supplies.